"GATE team on AMD AI League Hackathon"
Team Idea
Project: Cache-Resident Latent Reasoning Engine Architecture: * Input: Frozen LLM encodes the prompt into latent vectors. * Core Engine: A single Transformer JEPA block recurrently loops over latents to simulate multi-step logic. It applies distinct DoRA adapters per layer pass to steer reasoning at each step without representation collapse. * Output: Frozen LLM translates the final thought vectors back into text. Hardware Strategy (MI355X/MI350X) * Goal: Fit the entire training loop inside the 256MB Infinity Cache to completely bypass HBM bandwidth limits. * Compression Stack: * Recurrent Reuse + DoRA: Caches just one base Transformer block; only the lightweight, step-specific DoRA adapters swap per iteration. * Precision: FP4 (0.5 bytes/parameter). * Optimizer: GaLore (low-rank gradient projection cuts optimizer footprint by 90%). * Result: Near 100% FLOPs utilization and massively accelerated training due to zero VRAM memory stalling.
Submission
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