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POLYFORGE
__Long description (1998 chars):__ POLYFORGE is an AI-powered CUDA-to-any-hardware compiler pipeline that solves the cross-architecture portability problem. Drop in a standard CUDA kernel and POLYFORGE handles the rest through a 5-stage pipeline: 1. __LLM Comprehension__ — Fireworks AI Kimi-2.6 reads raw CUDA source and extracts a structured IR (intermediate representation), understanding thread indexing, synchronization, and memory patterns. A regex fallback ensures no kernel is ever silently dropped. 2. __Zero-Trust Oracle__ — An independent Clang AST simulator mathematically verifies every thread's execution before touching silicon. It catches LLM hallucinations, data races (RAW/WAR hazards), and correctness bugs that hardware testing alone can't reliably detect. The Oracle only hard-fails on real safety issues — limitations are gracefully skipped. 3. __Multi-Arch Code Lowering__ — Verified kernels are lowered to 5 hardware targets: Vortex RISC-V GPU, x86-64 (pthreads), ARM Cortex-A72 (NEON), ARM Cortex-M0, and generic RISC-V. Each target gets optimized C++ with correct parallelism emulation. 4. __Hardware Execution__ — Kernels compile and run on real hardware via WSL (Vortex SIMX for RISC-V, g++ for x86, QEMU for ARM). All output streams live for 100% transparency. 5. __RTL Capability Analysis__ — Scans Verilog/SystemVerilog for thread_id, parallel_spawn, barrier_sync, and addressable_memory primitives to verify hardware can actually run the kernel. The web playground provides an interactive interface with code editor, file uploads, terminal output, a Diagnosis panel that explains issues in plain English with fix suggestions, and architecture comparison tables. Built for the AMD Developer Hackathon.
13 Jul 2026
