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Manas Kulkarni@manaskulkarni02
1
Events attended
1
Submissions made
3+ years of experience
About me
Driven by the challenge of turning complex hardware problems into reliable, high-impact engineering solutions, my journey has taken me from leading embedded systems development for a Formula Student electric race car, to designing and validating high-reliability circuits for nuclear data acquisition systems, to working on GPU physical design at Intel. Across each step, I’ve been drawn to roles at the intersection of deep technical problem-solving, system-level thinking, and real-world execution. At Orion Racing India, I worked on the embedded systems backbone of an electric race car, including ECU hardware development, signal conditioning, CAN communication, telemetry, and data acquisition. At SLB, I contributed to hardware designed for harsh environments, including 175°C-rated circuit applications, where reliability and validation were critical. These experiences built a strong foundation in hardware design, testing, and system integration. That foundation led me deeper into chip design and silicon implementation. During my MSE in Electrical Engineering at the University of Pennsylvania, I worked on projects spanning digital VLSI, analog circuits, computer architecture, and low-power design, including the RTL-to-GDSII implementation of a low-power RISC-V processor. Today at Intel, I work on GPU physical design signoff, design methodology, debug, and automation, helping improve flow robustness and solving timing and power integrity challenges in advanced-node silicon. I’m particularly interested in physical design, signoff, low-power VLSI, circuit design, and AI in EDA, especially where smarter tools and automation can improve how chips and systems are designed, analyzed, and debugged. Feel free to connect if you’d like to discuss any of these areas.
🤝 Top Collaborators
🤓 Latest Submissions
Spice_Wizard
Analog circuit design is a bottleneck: unlike digital, it still depends on scarce senior engineers reading datasheets. LLMs can help, but they produce plausible text, not verified engineering a circuit can be mathematically correct and physically impossible. In one real run, GPT-5 made the textbook-correct resistor change and the simulation still failed, because the part's slew rate can't deliver that gain at that frequency. Only a simulator catches this, so we made the simulator the gatekeeper. Spice Wizard retrieves a known-good netlist from 4,032 indexed ADI application circuits, adapts component values using Qwen3 running on an AMD Instinct MI300X (PyTorch/ROCm), then verifies the result in real LTspice measuring gain, −3 dB bandwidth, phase, and settling against the spec with pass/fail margins. Failures feed measured evidence back for a retry. A best-of-N Candidate Arena validates topology invariants, ranks candidates by measured results, and exports an evidence bundle. Every verified pass is logged, building a simulation-labeled dataset for fine-tuning on the same MI300X a self-improving flywheel.
13 Jul 2026
