Chiplet-Aware Compilation for 3.5D Architectures

Developing a hardware-aware compiler that takes an application workload or machine learning model and a chiplet-based architecture as inputs to generate an optimized execution strategy tailored to the target hardware. The compiler jointly optimizes workload partitioning, operator mapping, computation placement, data movement, and memory hierarchy utilization across heterogeneous chiplets. Particular emphasis is placed on cross-chiplet communication optimization, including minimizing inter-chiplet data transfers, reducing communication latency and energy consumption, and optimizing bandwidth utilization across chiplet interconnects. By considering the architectural characteristics of 2.5D and 3D integration, including chiplet connectivity, interconnect topology, memory placement, and thermal constraints, the compiler aims to improve end-to-end execution latency, throughput, power efficiency, and heat dissipation. The ultimate goal is to bridge the gap between high-level workload representations and emerging chiplet-based hardware through compiler-driven, architecture-aware optimization.