Modern distributed AI workloads frequently move large tensors between GPUs, and communication can quickly become a major performance bottleneck.Analyzes the underlying machine topology—including GPU-to-GPU links, PCIe paths, NUMA placement, network bandwidth, and inter-node connectivity—and selects an appropriate communication schedule for the current workload. The initial MVP implements FP32 AllReduce using two different communication strategies: Ring AllReduce and a hierarchical Tree-based AllReduce. The runtime supports chunk pipelining, asynchronous communication, CUDA streams, overlapping computation with data transfers, timeout handling, and configurable transport layers such as sockets or UCX. The system runs across four GPUs distributed over two hosts, while NVIDIA NCCL is used as both a correctness and performance baseline. benchmarks multiple tensor sizes, chunk configurations, pipeline depths, and network conditions to understand when each communication strategy performs best.
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